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  1 ? fn6584.1 isl54066 negative signal swing, high off-isolation, dual spst single supply switch the intersil isl54066 device is a low on-resistance, high off-isolation, low voltage, dual si ngle-pole/single-throw (spst) analog switch. it was designed to operate from a single +1.8v to +6.5v supply and can pass signals that swing down to 6.5v below the positive supply rail. targeted applications include battery powered equipment that benefit from low r on (1 ), high off-isolation (80db) an d fast switching speeds (t on = 40ns, t off = 30ns). the digital logic input is 1.8v logic-compatible when using a single +3v supply. the isl54066 incorporates a t- switch architecture. this approach results in excellent signal off-isolation while retaining a low impedance signal path when switches are on. the isl54066 is offered in sm all form factor packages, alleviating board space limitations. the isl54066 is available in 10ld tqfn and tdfn packages. the isl54066 is a dual single-pole/single-throw (spst) normally open (no) switch with independent logic control. features ? pb-free (rohs compliant) ? negative signal swing (max 6.5v below v+) ? t-switch architecture ? on-resistance (r on ) - v+ = +4.5v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - v+ = +4.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - v+ = +2.7v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 - v+ = +1.8v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ?r on matching between channels . . . . . . . . . . . . . . . . . 10m ?r on flatness across signal range . . . . . . . . . . . . . . . . . 0.2 ? single supply operation . . . . . . . . . . . . . . . . .+1.8v to +6.5v ? low power consumption @ 3v (p d ). . . . . . . . . . . . 60nw ? fast switching action (v+ = +4.3v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns ? esd hbm rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kv ? 1.8v logic compatible (+3v supply) ? low i+ current when vinh is not at the v+ rail ? available in 10 ld tqfn and 10 ld 3x3 tdfn applications ? battery powered, handheld, and portable equipment - cellular/mobile phones - pagers - laptops, notebooks, palmtops ? portable test and measurement ? medical equipment ? audio and video switching related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? table 1. features at a glance isl54066 number of switches 2 switch type spst no 4.3v r on 1 4.3v t on /t off 40ns/30ns 2.7v r on 1.5 2.7v t on /t off 60ns/30ns 1.8v r on 3 1.8v t on /t off 180ns/44ns packages 10 ld tqfn, 10 ld tdfn r on ( ) v com (v) 012 345 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 -1 -2 -3 -4 -5 -6 i com = 100ma v+ = 1.8v v+ = 2.7v v+ = 4.5v on-resistance vs supply voltage vs switch voltage data sheet november 3, 2009 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6584.1 november 3, 2009 pinouts (note 1) isl54066 (10 ld tdfn) top view isl54066 (10 ld tqfn) top view note: 1. switches shown for ctlx = logic ?0?. logic ?0? 0.5v. logic ?1? 1.4v with a 3v supply. v+ in1 gnd1 out1 ctl1 gnd3 in2 gnd2 out2 ctl2 1 2 3 4 5 10 9 8 7 6 10k 10k 200k 200k 200k 10k ctl1 ctl2 out2 gnd2 in2 out1 gnd1 in1 v+ gnd3 12 3 4 5 10 9 8 7 6 200k 10k truth table ctlx inx/outx 0 open 1closed note: logic ?0? 0.5v. logic ?1? 1.4v with a 3v supply. pin descriptions pin function v+ system power supply input (+1.8v to +6.5v) gnd1 10k input shunt ground gnd2 200k output shunt ground gnd3 ic ground connection ctlx digital control input inx switch x input outx switch x output ordering information part number part marking temp. range (c) package (pb-free) pkg. dwg. # isl54066irz (note 3) 4066 -40 to +85 10 ld 3x3 tdfn l10.3x3a isl54066irz-t (notes 2, 3) 4066 -40 to +85 10 ld 3x3 tdfn (tape and reel) l10.3x3a ISL54066IRUZ-T (notes 2, 4) 9 -40 to +85 10 ld tqfn (tape and reel) l10.1.8x1.4a notes: 2. please refer to tb347 for de tails on reel specifications. 3. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std- 020. 4. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and comp atible with both snpb and pb-free soldering operations. intersi l pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. isl54066
3 fn6584.1 november 3, 2009 absolute maximum rati ngs thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0v input voltages inx (note 5) . . . . . . . . . . . . . . . . . . . . . . . (v+ - 7v) to ((v+) + 0.5v) cntlx (note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) output voltages outx (note 5) . . . . . . . . . . . . . . . . . . . . . (v+ - 7v) to ((v+) + 0.5v) continuous current inx or outx. . . . . . . . . . . . . . . . . . . . . 300ma peak current inx or outx (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . . 500ma esd rating: human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400v charged device model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kv thermal resistance (typical) ja (c/w) jc (c/w) 10 ld 3x3 tdfn package (notes 6, 8) 55 18 10 ld tqfn package (note 7) . . . . . 155 n/a maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp) operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c power supply range . . . . . . . . . . . . . . . . . . . . . . . . +1.8v to +6.5v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. signals on nc, no, in, or com exceeding v+ or gnd by specified amount are clamped by internal diodes. limit forward diode cur rent to maximum current ratings. 6. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 7. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 8. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v ctl_h = 2.4v, v ctl_l = 0.8v (note 9), unless otherwise specified. parameter test conditions temp (c) min (notes 10, 11) typ max (notes 10, 11) units analog switch characteristics on-resistance, r on v+ = 4.5v, i out = 100ma, v in = (v+ - 6.5) to v+, (see figure 4) 25 - 1 - full - 1.2 - r on matching between channels, r on v+ = 4.5v, i out = 100ma, v in = voltage at max r on, (note 13) 25 - 5 - m full - 10 - m r on flatness, r flat(on) v+ = 4.5v, i out = 100ma, v in = (v+ - 6.5) to v+, (note 12) 25 - 0.21 - full - 0.27 - dynamic characteristics turn-on time, t on v+ = 4.5v, v in = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 39 - ns full - 46 - ns turn-off time, t off v+ = 4.5v, v in = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 27 - ns full - 33 - ns charge injection, q v g = 0v, r g = 0 , c l = 1.0nf (see figure 2) 25 - 170 - pc off-isolation r l = 50 , c l = 5pf, f = 1mhz, v inx = 1v rms (see figure 3) 25 - 70 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 1mhz, v in1 = 1v rms (see figure 5) 25 - -80 - db total harmonic distortion f = 20hz to 20khz, v out = 2v p-p , r l = 32 25 - 0.015 - % -3db bandwidth r l = 50 25 - 30 - mhz inx off capacitance, c off f = 1mhz, gnd1 = float (see figure 6) 25 - 33 - pf outx on capacitance, c out(on) f = 1mhz, gnd2 = float (see figure 6) 25 - 124 - pf power supply characteristics positive supply current, i+ v+ = +5.5v, v ctlx = 0v or v+ 25 - 0.03 0.1 a full - 1.64 - a isl54066
4 fn6584.1 november 3, 2009 digital input characteristics input voltage low, v ctlx_l full - - 0.8 v input voltage high, v ctlx_h full 2.4 - - v input current, i ctlx_h , i ctlx_l v+ = 5.5v, v ctlx = 0v or v+ 25 -0.1 - 0.1 a full - 0.9 - a electrical specifications - 4.3v supply test conditions: v+ = +3.9v to +4.5v, gnd = 0v, v ctl_h = 1.6v, v ctl_l = 0.5v (note 9), unless otherwise specified. parameter test conditions temp (c) min (notes 10, 11) typ max (notes 10, 11) units analog switch characteristics on-resistance, r on v+ = 4.3v, i out = 100ma, v in = (v+ - 6.5) to v+, (see figure 4) 25 - 1 - full - 1.2 - r on matching between channels, r on v+ = 4.3v, i out = 100ma, v in = voltage at max r on, (note 13) 25 - 5 - m full - 10 - m r on flatness, r flat(on) v+ = 4.3v, i out = 100ma, v in = (v+ - 6.5) to v+ (note 12, 14) 25 - 0.2 - full - 0.27 - dynamic characteristics turn-on time, t on v+ = 3.9v, v in = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 40 - ns full - 47 - ns turn-off time, t off v+ = 3.9v, v in = 3.0v, r l = 50 , c l = 35pf, (see figure 1) 25 - 31 - ns full - 34 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 , ( see figure 2) 25 - 200 - pc off-isolation r l = 50 , c l = 5pf, f = 1mhz, v inx = 1v rms (see figure 3) 25 - 70 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 1mhz, v in1 = 1v rms (see figure 5) 25 - -80 - db total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 32 25 - 0.02 - % inx off capacitance, c off f = 1mhz, gnd1 = float (see figure 6) 25 - 33 - pf outx on capacitance, c out(on) f = 1mhz, gnd2 = float (see figure 6) 25 - 124 - pf power supply characteristics positive supply current, i+ v+ = +4.5v, v ctlx = 0v or v+ 25 -0.02 0.1 a full -1.76 - a positive supply current, i+ v+ = +4.2v, v ctl1 = v ctl2 = 2.85v 25 -0.95 12 a digital input characteristics input voltage low, v ctlx_l full -- 0.5 v input voltage high, v ctlx_h full 1.6 -- v input current, i ctlx_h , i ctlx_l v+ = 4.5v, v ctlx = 0v or v+ 25 -0.5 - 0.5 a full - 0.63 - a electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v ctl_h = 2.4v, v ctl_l = 0.8v (note 9), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 10, 11) typ max (notes 10, 11) units isl54066
5 fn6584.1 november 3, 2009 electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v ctl_h = 1.4v, v ctl_l = 0.5v (note 9), unless otherwise specified. parameter test conditions temp (c) min (notes 10, 11) typ max (notes 10, 11) units analog switch characteristics on-resistance, r on v+ = 2.7v, i out = 100ma, v in = (v+ - 6.5) to v+ (see figure 4) 25 - 1.5 - full - 1.9 - r on matching between channels, r on v+ = 2.7v, i out = 100ma, v in = voltage at max r on, (note 13) 25 - 10 - m full - 10 - m r on flatness, r flat(on) v+ = 2.7v, i out = 100ma, v in = (v+ - 6.5) to v+ (notes 12, 14) 25 - 0.63 1 full - 0.68 1.35 dynamic characteristics turn-on time, t on v+ = 2.7v, v in = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 60 - ns full - 68 - ns turn-off time, t off v+ = 2.7v, v in = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 31 - ns full - 35 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 , ( see figure 2) 25 - 150 - pc off-isolation r l = 50 , c l = 5pf, f = 1mhz, v inx = 1v rms (see figure 3) 25 - 70 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 1mhz, v in1 = 1v rms (see figure 5) 25 - -80 - db total harmonic distortion f = 20hz to 20khz, v out = 2v p-p , r l = 32 25 - 0.04 - % inx off capacitance, c off f = 1mhz, gnd1 = float (see figure 6) 25 - 33 - pf outx on capacitance, c out(on) f = 1mhz, gnd2 = float (see figure 6) 25 - 124 - pf power supply characteristics positive supply current, i+ v+ = +3.6v, v ctlx = 0v or v+ 25 - 0.02 - a full - 1.76 - a digital input characteristics input voltage low, v ctlx_l 25 - - 0.5 v input voltage high, v ctlx_h 25 1.4 - - v input current, i ctlx_h , i ctlx_l v+ = 3.3v, v ctl x = 0v or v+ 25 -0.5 - 0.5 a full - 0.55 - a electrical specifications - 1.8v supply test conditions: v+ = +1.8v, gnd = 0v, v ctl_h = 1.0v, v ctl_l = 0.4v (note 9), unless otherwise specified. parameter test conditions temp (c) min (notes 10, 11) typ max (notes 10, 11) units analog switch characteristics on-resistance, r on v+ = 1.8v, i out = 100ma, v in = (v+ - 6.5v) to v+, (see figure 4) 25 - 3 - full - 3.2 - r on matching between channels, r on v+ = 1.8v, i out = 100ma, v in = voltage at max r on, (note 13) 25 - 20 - m full - 20 - m r on flatness, r flat(on) v+ = 1.8v, i out = 100ma, v in = (v+ - 6.5) to v+, (note 12) 25 - 2.3 - full - 2.5 - isl54066
6 fn6584.1 november 3, 2009 dynamic characteristics turn-on time, t on v+ = 1.8v, v in = 1.8v, r l = 50 , c l = 35pf (see figure 1) 25 - 180 - ns turn-off time, t off v+ = 1.8v, v in = 1.8v, r l = 50 , c l = 35pf (see figure 1) 25 - 44 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 , ( see figure 2) 25 - 40 - pc -3db bandwidth v com = 1v rms , r l = 50 , c l = 5pf 25 - 30 - mhz inx off capacitance, c off f = 1mhz, gnd1 = float (see figure 6) 25 - 33 - pf outx on capacitance, c out(on) f = 1mhz, gnd2 = float (see figure 6) 25 - 124 - pf digital input characteristics input voltage low, v ctlx_l 25 - - 0.4 v input voltage high, v ctlx_h 25 1.0 - - v input current, i ctlx_h , i ctlx_l v+ = 2.0v, v ctlx = 0v or v+ 25 -0.5 - - a full - 0.5 - a notes: 9. v ctl_x = input voltage to perform proper function. 10. the algebraic convention, whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. 11. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established b y characterization and are not production tested. 12. flatness is defined as the difference between maximum and minimum value of on-resis tance over the specified analog signal ra nge. 13. r on matching between channels is calculated by s ubtracting the channel with the highest max r on value from the channel with lowest max r on value, between in1 and in2. 14. limits established by characteri zation and are not production tested. test circuits and waveforms figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times electrical specifications - 1.8v supply test conditions: v+ = +1.8v, gnd = 0v, v ctl_h = 1.0v, v ctl_l = 0.4v (note 9), unless otherwise specified. (continued) parameter test conditions temp (c) min (notes 10, 11) typ max (notes 10, 11) units 50% t r < 5ns t f < 5ns t off 90% v+ 0v v in 0v t on logic input switch input switch output 90% v out v out v (in) r l r l r on + ----------------------- - = switch input logic input v out r l c l out in ctl 50 35pf gndx v+ c isl54066
7 fn6584.1 november 3, 2009 figure 2a. measurement points figure 2b. test circuit figure 2. charge injection figure 3. off-isolation test circuit figure 4. r on test circuit figure 5. crosstalk test circuit figure 6. capacitance test circuit test circuits and waveforms (continued) v out v out on off on q = v out x c l switch output logic input v+ 0v c l v out r g v g gndx outx inx v+ c logic input ctlx repeat test for all switches. analyzer r l signal generator v+ c 0v inx outx ctlx gndx *50 source v+ c v+ inx outx ctlx gndx v in v 1 r on = v 1 /100ma 100ma repeat test for all switches. v+ analyzer v+ c in1 signal generator r l gndx ctl1 out1 50 out2 in2 *50 source v+ c gnd3 inx outx ctlx impedance analyzer 0v or v+ *float gnd1 and gnd2 isl54066
8 fn6584.1 november 3, 2009 the isl54066 is a dual single pole-single throw (spst) analog switch that offers prec ise switching from a single 1.8v to 6.5v supply with low on-resistance (1.5 ), high off-isolation, high speed operation (t on = 60ns, t off = 30ns) and negative signal swing capability. the device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8v), low power consumption (30na), and a tiny 1.8mmx 1.4mm tqfn package or a 3mmx3mm tdfn package. the low r on resistance and r on flatness provide very low insertion loss and signal distortion for applications that require signal switching with minimal interference by the switch. in additon, the isl54066 uses a t-switch architecture to achieve superior off-isolation from the input to output of the switch. input/output shunt resistors the isl54066 contains input and output shunts resistors on the switch terminals. on the inx pins, there are 10k shunts to the gnd1 pin. on the outx pins, there are 200k shunts to the gnd2 pin. the input sh unts are designed to discharge voltage that may be built up on the input pins, such as dc offsets due to ac-coupled signals. the output shunts are designed to bleed off any charge that may accumulate on the output pins when the switch is turned off. to have the shunt resistors enabled, connect the gnd1 and gnd2 pins to gnd3. the gnd3 pin is the main ground of the isl54066 ic. the shunt resistors can be disconnected from the ic by floating the appropriate gnd1 and gnd2 pin. grounding considerations for maximum off-isolation performance, it is recommended to follow a star ground configuration of the gndx pins (see figure 7). grounding the g nd1, gnd2 and gnd3 pins to a star ground ensures ther e are no cross conduction of ground currents between the ground pins, which effect the off-isolation capability of the switch. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to gnd (see figure 8). to prevent forward biasing these diodes, v+ must be applied before any input signals, and the input signal voltages must remain between (v + - 6.5v) and v+. if these conditions cannot be guaranteed, then precautions must be implemented to prohib it the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. the following two methods can be used to provided additional protection to limit the current in the event that the voltage at a logic pin or switch terminal goes above the v+ rail. logic inputs can be protected by adding a 1k resistor in series with the logic input (see figure 8). the resistor limits the input current below the threshold that produces permanent damage. this method is not acceptable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch. alternatively, connecting external schottky diodes from the v+ rail to the signal pins will shunt the fault current through the schottky diode instead of through the internal esd diodes, thereby protecting the switch. these schottky diodes must be sized to handle the expected fault current.. power-supply considerations the isl54066 construction is ty pical of most single supply cmos analog switches which ha ve two supply pins: v+ and gnd. v+ and gnd provide the cmos switch bias and sets their analog voltage limits. unlike switches with a 5.5v maximum supply voltage, the isl54066 have a 6.5v maximum supply voltage providing plenty of head room for the 10% tolerance of 5v supplies due to overshoot and noise spikes. the minimum recommended supply voltage is +1.8v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the ?electrical specifications? tables, beginning on page 3 and ?typical performance curves?, beginning on page 10 for details. isl54066 in1 in2 ctl1 gnd3 vdd ctl2 v+ 0.1f gnd1 gnd2 out1 out2 figure 7. star grounding configuration gnd v inx v+ logic inputs v outx -ring +ring clamp 1k figure 8. overvoltage protection isl54066
9 fn6584.1 november 3, 2009 v+ and gnd also power the internal logic and level shifters. the level shifters convert the input logic levels to v+ and gnd signals levels to drive the analog switch gate terminals. a high frequency decoupling capacitor placed as close to the v+ and gnd pin as possible is recommended for proper operation of the switch. a value of 0.1f is highly recommended. negative signal swing capability the isl54066 contains circuitry that allows the analog switch signal to swing below ground. the device has an analog signal range of 6.5v below v+ up to the v+ rail (see figure 14) while maintaining low r on performance. for example, if v+ = 5v, then the analog input signal range is from -1.5v to +5v. if v+ = 2.7v then the range is from -3.8v to +2.7v. logic-level thresholds this switch family is 1.8v cmos compatible (0.45v v olmax and 1.35v v ohmin ) over a supply range of 1.8v to 3.3v (see figure 16). at 3.3v the v il level is 0.5v maximum. this is still below the 1.8v cmos guaranteed low output maximum level of 0.45v, but noise margin is reduced. at 3.3v the v ih level is 1.4v minimum. while this is above the 1.8v cmos guaranteed high output minimum of 1.35v under most operating conditi ons the switch will recognize this as a valid logic high. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from gn d to v+ with a fast transition time minimizes power dissipation. the isl54066 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0v to v+). for example, driving the device with 2.85v logic high while operating with a 4.2v supply, th e device draws only 1a of current. high-frequency performance in 50 systems, the isl54066 has a -3db bandwidth of 30mhz (see figure 19). the frequency response is very consistent over a wide v+ range and for varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch?s input to its output. off-isolation is the resistance to this feed-through, while crosstalk indicates the amount of feedthrough from one switch to another. figure 20 details the high off-isolation and crosstalk rejection provided by this part. at 1mhz, off-isolation is approximately 70db in 50 systems, decreasing approximately 4 0db per decade as frequency increases. crosstalk is approximately -80db at 1mhz in 50 systems. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin, v+ and gnd. one of these diodes conducts if any analog signal exceeds the recommended analog signal range. virtually all the analog switch leakage current comes from the esd diodes and reversed bi ased junctions in the switch cell. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased to either the +ring or -ring and the analog input signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the +ring or -ring and the reverse biased junctions at the internal switch cell constitutes the analog-signal-path leakage current. isl54066
10 fn6584.1 november 3, 2009 typical performance curves t a = +25c, unless otherwise specified figure 9. on-resistance vs supply voltage vs switch voltage figure 10. on-resistance vs switch voltage figure 11. on-resistance vs switch voltage figure 12. on-resistance vs switch voltage figure 13. on-resistance vs switch voltage figure 14. analog signal range vs supply voltage r on ( ) v com (v) 0 12 3 4 5 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 -1 -2 -3 -4 -5 -6 i com = 100ma v+ = 1.8v v+ = 2.7v v+ = 4.5v r on ( ) v out (v) 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -3 -2 -1 0 1 2 3 4 5 i out = 100ma v+ = 4.5v t = +25c t = +85c t = -40c r on ( ) v out (v) 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 -3-2-1012345 i out = 100ma v+ = 4.3v t = +25c t = +85c t = -40c r on ( ) v out (v) 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 -5 -4 -3 -2 -1 0 1 2 3 4 i out = 100ma v+ = 2.7v t = +25c t = +85c t = -40c r on ( ) v out (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -6-5-4-3-2-10123 i out = 100ma v+ = 1.8v t = 25c t = 85c t = -40c -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 analog signal range (v) signal max signal min supply voltage (v) isl54066
11 fn6584.1 november 3, 2009 figure 15. charge inject ion vs switch voltage figure 16. digital switching point vs supply voltage figure 17. turn-on time vs supply voltage figure 18. turn-off time vs supply voltage figure 19. frequency response figure 20. crosstalk and off-isolation typical performance curves t a = +25c, unless otherwise specified (continued) q (pc) v com (v) 0 50 100 150 012345 -1 -2 -3 -4 -5 6 v+ = 4.5v v+ = 3.3v v+ = 2.0v absolute values v+ = 5.5v 200 250 300 350 400 450 500 550 600 650 700 absolute values v+ (v) 1.52.02.53.03.54.04.5 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 v ctl_h v ctl_l 0.2 0.1 0 1.6 1.5 1.4 1.3 1.2 v ctl_h and v ctl_l t on (ns) v+ (v) t = +85c t = -40c t = +25c 1.8 3.3 4.5 5.5 0 20 40 60 80 100 120 140 160 t off (ns) v+ (v) 1.8 3.3 4.5 5.5 0 20 40 5 10 15 25 30 35 t = +85c t = -40c t = +25c frequency (hz) normalized gain (db) -8 -7 -6 -5 -4 -3 -2 -1 0 1 1k 100k 1m 100m 10k 10m 1g v in = 1vrms @ 0vdc offset r l = 50 v+ = 1.8v to 5.5v frequency (hz) 1k 100k 1m 100m 1g 10k 10m crosstalk (db) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 off-isolation crosstalk v in = 1vrms @ 0vdc offset r l = 50 v+ = 1.8v to 5.5v isl54066
12 fn6584.1 november 3, 2009 figure 21. total harmonic distortion vs frequency die characteristics substrate potential (powered up): gnd (dfn paddle connection: tie to gnd or float) transistor count: 432 process: submicron cmos typical performance curves t a = +25c, unless otherwise specified (continued) frequency (hz) thd+n (%) v bias = 0vdc r l = 32 v+ = 3.3v 707mv rms 360mv rms 177mv rms 20 100 200 1k 2k 10k 20k 0.01 0.02 0.03 0.04 0.05 0 0.06 0.07 0.08 0.09 isl54066
13 fn6584.1 november 3, 2009 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x c 0.05 c a 0.10 c a1 seating plane index area 2 1 n top view side view nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x l1 e nx l bottom view 5 7 2 1 pin #1 id (datum a) (datum b) 0.10 m c a b 0.05 m c nx b 10x 5 0.50 0.20 0.40 1.80 0.40 0.20 2.20 1.00 0.60 1.00 land pattern 10 l10.1.8x1.4a 10 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 1.75 1.80 1.85 - e 1.35 1.40 1.45 - e 0.40 bsc - l 0.35 0.40 0.45 - l1 0.45 0.50 0.55 - n102 nd 2 3 ne 3 3 0- 12 4 rev. 3 6/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389. isl54066
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6584.1 november 3, 2009 isl54066 thin dual flat no-lead plastic package (tdfn) // nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.10 2x e a b c 0.10 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k l1 9 l m l10.3x3a 10 lead thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.30 5, 8 d 2.95 3.0 3.05 - d2 2.25 2.30 2.35 7, 8 e 2.95 3.0 3.05 - e2 1.45 1.50 1.55 7, 8 e 0.50 bsc - k 0.25 - - - l 0.25 0.30 0.35 8 n 10 2 nd 5 3 rev. 3 3/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-weed-3 except for d2 dimensions.


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